The present invention relates to the generation of complementary clock signals with non-overlapping phases at twice the frequency of an input clock signal.
Before describing the invention, the operation of a clock generator with non-overlapping phases comprising NAND gates, further called NAND flip-flop will be reminded. It will be noted that this flip flop is different of a conventional RS flip-flop made with NOR gates.
FIG. 1A schematically shows an NAND flip-flop 1 comprising two input terminals E1 and E2 and two complementary outputs Q* and Q. This flip flop includes two NAND gates A1 and A2. The first input of gate A1 is connected to terminal E1 and the second input to output Q of gate A2. The first input of gate A2 is connected to terminal E2 and the second input to the complementary output Q* of gate A1. Inputs E1 and E2 respectively receive a clock signal CLK and the complementary signal CLK*
FIG. 1B shows the shape of the signals at the inputs and outputs. Considering a state where the input clock CLK is low, CLK* is high, Q* is high and Q is low. When CLK* goes low, the NAND gate A2 changes its state and signal Q goes high after a delay depending upon the structure of gate A1. This switching of the output Q causes switching of gate A1 and signal Q* goes low after a second delay.
It will be noted, as known in the art, that the delay caused by a high/low switching such as the one of output Q* may be different of the delay associated with a high/low switching such as the one of output Q.
Then, when the signal CLK goes high, the transition to low level of signal CLK causes the switching of gate A1 and the transition to high level of output Q* after the first delay, while gate A2 then switches after the second delay to allow output Q to go low. Then, signals Q and Q* having the same period as the input clock signals CLK and CLK* are obtained, but the phases during which these signals Q and Q are at low level are not overlapping. It is said that clock signals with non-overlapping low phases have been generated.
An object of the invention is to provide a circuit particularly simple and fully integrable for providing, from an input clock signal, complementary non overlapping clock signals with double frequency.
A further object of the invention is to provide a simple and integrable circuit for providing, from an input clock signal, on the one hand, non overlapping clock signals of equal frequency and, on the other hand, non overlapping clock signals of double frequency, a determined phase relationship being established between the single frequency and double frequency signals.